Figure 16.4.1
The transistors in the CMOS inverter in Fig. 16.4.1 have $k_{n}^{\prime}(W / L)_{n}=k_{p}^{\prime}(W / L)_{p}=10 \mathrm{~mA} / \mathrm{V}^{2},\left|V_{t}\right|=$ $1 \mathrm{~V}$, and $\lambda=0$.
(a) What is the value of the gate threshold?
(b) For $v_{I}=0 \mathrm{~V}$, what is the resistance between the output terminal and the $V_{D D}$ supply? If a resistance $R_{L}=1 \mathrm{k} \Omega$ is connected between the output terminal and ground, what will $v_{O}$ be?

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Figure 16.4.1
The transistors in the CMOS inverter in Fig. 16.4.1 have $k_{n}^{\prime}(W / L)_{n}=k_{p}^{\prime}(W / L)_{p}=10 \mathrm{~mA} / \mathrm{V}^{2},\left|V_{t}\right|=$ $1 \mathrm{~V}$, and $\lambda=0$.
(a) What is the value of the gate threshold?
(b) For $v_{I}=0 \mathrm{~V}$, what is the resistance between the output terminal and the $V_{D D}$ supply? If a resistance $R_{L}=1 \mathrm{k} \Omega$ is connected between the output terminal and ground, what will $v_{O}$ be?

Figure 164 kn′(W/L)n=kp′(W/L)p=10 mA/V2,∣Vt∣=k_{n}^{\prime}(W / L)_{n}=k_{p}^{\prime}(W / L)_{p}=10 \mathrm{~mA} / \mathrm{V}^{2},\left|V_{t}\right|=kn′​(W/L)n​=kp′​(W/L)p​=10 mA/V2,∣Vt​∣= 1 V1 \mathrm{~V}1 V

Figure 164 $k_{n}^{\prime}(W / L)_{n}=k_{p}^{\prime}(W / L)_{p}=10 \mathrm{~mA} / \mathrm{V}^{2},\left|V_{t}\right|=$ $1 \mathrm{~V}$