The CMOS inverter shown in Fig. 16.2.1 has $V_{D D}=1.8 \mathrm{~V}$ and is fabricated in a $0.18-\mu \mathrm{m}$ process for which $\mu_{n}=4 \mu_{p}, \mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2}$, and $V_{t n}=-V_{t p}=0.4 \mathrm{~V}$. For this problem, neglect the Early effect. Both $Q_{N}$ and $Q_{P}$ use the minimum channel length allowed. For $Q_{N}, W / L=1.5$.
(a) Find the dimensions that $Q_{P}$ must have in order for the inverter switching to occur at $v_{I}=0.9 \mathrm{~V}$.
(b) What are the noise margins of the inverter?
(c) What current flows in $Q_{N}$ and $Q_{P}$ at the switching point?
(d) For $v_{I}=1.8 \mathrm{~V}$, what is the maximum current that $Q_{N}$ can sink while $v_{O}$ is limited to $0.4 \mathrm{~V}$ ?

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The CMOS inverter shown in Fig. 16.2.1 has $V_{D D}=1.8 \mathrm{~V}$ and is fabricated in a $0.18-\mu \mathrm{m}$ process for which $\mu_{n}=4 \mu_{p}, \mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2}$, and $V_{t n}=-V_{t p}=0.4 \mathrm{~V}$. For this problem, neglect the Early effect. Both $Q_{N}$ and $Q_{P}$ use the minimum channel length allowed. For $Q_{N}, W / L=1.5$.
(a) Find the dimensions that $Q_{P}$ must have in order for the inverter switching to occur at $v_{I}=0.9 \mathrm{~V}$.
(b) What are the noise margins of the inverter?
(c) What current flows in $Q_{N}$ and $Q_{P}$ at the switching point?
(d) For $v_{I}=1.8 \mathrm{~V}$, what is the maximum current that $Q_{N}$ can sink while $v_{O}$ is limited to $0.4 \mathrm{~V}$ ?

The CMOS Inverter Shown in Fig VDD=1.8 VV_{D D}=1.8 \mathrm{~V}VDD​=1.8 V And Is Fabricated in A

The CMOS Inverter Shown in Fig $V_{D D}=1.8 \mathrm{~V}$ And Is Fabricated in A