Question 1

A buffer for an I/O device is typically implemented on the sending computer.

Accepted Answer

A buffer for an I/O device is typically implemented on the receiving computer or within the I/O device itself to manage the flow of data and accommodate speed differences between the device and the computer.

Question 2

When multiple processors occupy a single motherboard, they share primary storage and a single system bus.

Accepted Answer

When multiple processors occupy a single motherboard, they share primary storage and a single system bus.

Question 3

Secondary storage devices are much faster than the system bus.

Accepted Answer

Secondary storage devices are typically slower than the system bus. While secondary storage devices have large storage capacities, they are not optimized for quick data transfer or system operations like the system bus.

Question 4

Disk caching is common in modern computer systems, particularly in file and database servers.

Accepted Answer

Disk caching is indeed common in modern computer systems, particularly in file and database servers. Disk caching involves storing frequently accessed data in a portion of the computer's RAM to speed up data access times, which can significantly improve overall system performance.

Question 5

A system bus can be conceptually or physically divided into specialized subsets, including the data, address, control, and power buses.

Accepted Answer

This statement is true. A system bus is typically divided into these subsets to manage different types of data and signals. The data bus carries actual data between components, the address bus specifies which memory location or device is being accessed, the control bus carries commands and status signals, and the power bus delivers electrical power to components.

Question 6

The CPU communicates with a peripheral device by moving data to or from an I/O port's dedicated bus.

Accepted Answer

The answer of The CPU communicates with a peripheral device...

Question 7

A full-featured 64-bit CPU, even one with multiple ALUs and pipelined processing, typically requires fewer than 50 million transistors.

Accepted Answer

Modern 64-bit CPUs, especially those with multiple Arithmetic Logic Units (ALUs), pipelined processing, and other advanced features, often require hundreds of millions to billions of transistors. For example, Intel and AMD CPUs in the consumer market have long surpassed the 50 million transistor count, with some models featuring over a billion transistors to support their complex architectures and capabilities.

Question 8

A PC usually transmits data one bit at a time over a wireless connection, and a laser printer prints an entire page at once.

Accepted Answer

A PC usually transmits data one bit at a time over a wireless connection, while a laser printer prints an entire page at once.

Question 9

​A system bus connects computer system components, including the CPU, memory, storage, and I/O devices.

Accepted Answer

A system bus is responsible for connecting various computer system components, including the CPU, memory, storage, and I/O devices, and facilitating communication between them.

Question 10

​Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement.

Accepted Answer

Performance is actually improved if storage and I/O devices can transmit data between themselves without explicit CPU involvement. This is known as DMA (Direct Memory Access) and it allows data to be transferred directly between devices without having to be processed by the CPU. This frees up the CPU to focus on other tasks and can significantly improve overall system performance.

Question 11

Peer-to-peer bus protocols are substantially less complex but more expensive than master-slave bus protocols.

Accepted Answer

Peer-to-peer bus protocols are actually less expensive than master-slave bus protocols because they do not require a dedicated master device, which can be costly. Additionally, peer-to-peer protocols can be more flexible and scalable since any device can communicate directly with any other device on the bus without going through a central controller. However, they may be less efficient in terms of bandwidth utilization and may require more complex routing algorithms.

Question 12

During a write operation, a cache acts similarly to a buffer.

Accepted Answer

During a write operation, data is first written to the cache before it is written to the main memory. This is done to improve performance as the cache is faster than the main memory. Similarly, a buffer is also used to hold data temporarily before it is written to a file or transferred over a network. Therefore, a cache and a buffer act similarly during a write operation.

Question 13

The OS is the best source of file access information because it updates information dynamically as it services file access requests.

Accepted Answer

This statement is true. The operating system keeps track of file access information and updates it dynamically as it services access requests from various applications and user accounts. This ensures that the most up-to-date information about file access permissions and security settings is always available to the system and its users.

Question 14

Data written to a cache during a write operation isn't automatically removed from the cache after it's written to the underlying storage device.

Accepted Answer

Data written to a cache during a write operation is not automatically removed from the cache after it's written to the underlying storage device. The cache may hold onto the data for faster read access in the future.

Question 15

With serial communication lines in a bus, each line carries only one bit value or signal at a time, and many lines are required to carry data, address, and control bits.

Accepted Answer

In serial communication, data is sent sequentially one bit at a time over a single communication line, rather than using multiple lines for parallel transmission of data bits.

Question 16

Until the 2000s, system buses were always constructed with serial electrical lines.

Accepted Answer

Until the 2000s, system buses were constructed with parallel electrical lines, not serial. Serial buses became more common with the introduction of technologies such as USB and SATA.

Question 17

One way to limit wait states is to use an SDRAM cache between the CPU and SRAM primary storage.

Accepted Answer

SDRAM is a type of DRAM, not a cache, and it typically serves as main system memory rather than a cache between the CPU and SRAM. SRAM is faster than SDRAM and is often used for the cache itself.

Question 18

The memory bus has a much higher data transfer rate than the system bus because of its shorter length, higher clock rate, and (in most computers) large number of parallel communication lines.

Accepted Answer

The memory bus is designed to transfer data between the CPU and memory much faster than the system bus which connects all the components of the computer. The memory bus has a shorter length, higher clock rate, and more parallel communication lines, all of which contribute to its higher data transfer rate.

Question 19

Serial channels in buses are more reliable than parallel channels at very high speeds.

Accepted Answer

At very high speeds, parallel channels are susceptible to interference, crosstalk, and synchronization issues, while serial channels can provide more reliable communication by transmitting data one bit at a time.

Question 20

Devices with low data transfer demand can use a single PCI bus lane, and devices with higher requirements can increase their available data transfer rate by using additional lanes.

Accepted Answer

This statement is true. PCI (Peripheral Component Interconnect) technology allows devices to use one or more lanes for data transfer. Each lane provides a certain amount of data transfer capacity, so devices with higher data transfer requirements can use multiple lanes to increase their available bandwidth. This allows for flexible scalability and helps to optimize performance for different devices and applications.

Quiz 6: System Integration and Performance

A buffer for an I/O device is typically implemented on the sending computer.

When multiple processors occupy a single motherboard, they share primary storage and a single system bus.

Secondary storage devices are much faster than the system bus.

Disk caching is common in modern computer systems, particularly in file and database servers.

A system bus can be conceptually or physically divided into specialized subsets, including the data, address, control, and power buses.

The CPU communicates with a peripheral device by moving data to or from an I/O port's dedicated bus.

A full-featured 64-bit CPU, even one with multiple ALUs and pipelined processing, typically requires fewer than 50 million transistors.

A PC usually transmits data one bit at a time over a wireless connection, and a laser printer prints an entire page at once.

​A system bus connects computer system components, including the CPU, memory, storage, and I/O devices.

​Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement.

Peer-to-peer bus protocols are substantially less complex but more expensive than master-slave bus protocols.

During a write operation, a cache acts similarly to a buffer.

The OS is the best source of file access information because it updates information dynamically as it services file access requests.

Data written to a cache during a write operation isn't automatically removed from the cache after it's written to the underlying storage device.

With serial communication lines in a bus, each line carries only one bit value or signal at a time, and many lines are required to carry data, address, and control bits.

Until the 2000s, system buses were always constructed with serial electrical lines.

One way to limit wait states is to use an SDRAM cache between the CPU and SRAM primary storage.

The memory bus has a much higher data transfer rate than the system bus because of its shorter length, higher clock rate, and (in most computers) large number of parallel communication lines.

Serial channels in buses are more reliable than parallel channels at very high speeds.

Devices with low data transfer demand can use a single PCI bus lane, and devices with higher requirements can increase their available data transfer rate by using additional lanes.

A system bus connects computer system components, including the CPU, memory, storage, and I/O devices.

Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement.