Figure 8.3.1
Design the double-cascode current source shown in Fig. 8.3.1 to provide $I=0.2 \mathrm{~mA}$ and the largest possible signal swing at the output; that is, design for the minimum allowable voltage across each transistor. The CMOS fabrication process available has $\left|V_{t p}\right|=0.4 \mathrm{~V},\left|V_{A}^{\prime}\right|=6 \mathrm{~V} / \mu \mathrm{m}$, and $\mu_{p} C_{o x}=100 \mu \mathrm{A} / \mathrm{V}^{2}$. Use devices with $L=$ $0.4 \mu \mathrm{m}$, and operate at $\left|V_{O V}\right|=0.2 \mathrm{~V}$.
(a) Specify $V_{G 1}, V_{G 2}$, and $V_{G 3}$.
(b) Find the $W / L$ ratios of the transistors.
(c) What is the value of $R_{O}$ achieved?
(d) What is the maximum allowable voltage at the current-source output?
(e) If this current source is used as the load of an NMOS double-cascode amplifier having a shortcircuit transconductance of $2 \mathrm{~mA} / \mathrm{V}$ and an output resistance equal to $R_{O}$ of the current source, what voltage gain is obtained?

Question

Quizplus · Accepted Answer

The Answer is $Figure 8.3.2 (a) Refer to Figure 8.3.2. For \left|V_{t p} ight|=0.4 \mathrm{~V} and \left|V_{O V} ight|=0.2 \mathrm{~V}, V_{S G}=0.6 \mathrm{~V} and the minimum required V_{S D} for each transistor is 0.2 \mathrm{~V} . Thus, V_{G 1}=+1.2 \mathrm{~V}, \quad V_{G 2}=+1.0 \mathrm{~V}, \quad and \quad V_{G S}=+0.8 \mathrm{~V} (b) \begin{aligned} I_{D} & =\frac{1}{2} \mu_{p} C_{O x}\left(\frac{W}{L} ight)\left|V_{O V} ight|^{2} \ 0.2 & =\frac{1}{2} imes 0.1 imes \frac{W}{L} imes 0.2^{2} \ \Rightarrow \frac{W}{L} & =100 \end{aligned} (c) \begin{aligned} r_{o 1} & =\frac{\left|V_{A} ight|}{I_{D}}=\frac{\left|V_{A}^{\prime} ight| L}{I_{D}}=\frac{6 imes 0.4}{0.2}=12 \mathrm{k} \Omega \ r_{o 2} & =r_{o 3}=r_{o 1}=12 \mathrm{k} \Omega \ g_{m 2} & =g_{m 3}=\frac{2 I_{D}}{\left|V_{O V} ight|}=\frac{2 imes 0.2}{0.2}=2 \mathrm{~mA} / \mathrm{V} \ R_{o 2} & =\left(g_{m 2} r_{o 2} ight) r_{o 1}=(2 imes 12) imes 12=288 \mathrm{k} \Omega \ R_{o 3} & =\left(g_{m 3} r_{o 3} ight) R_{o 2}=(2 imes 12) imes 288=6912 \mathrm{k} \Omega \end{aligned} (d) v_{O \max }=0.8+0.4=+1.2 \mathrm{~V} (e) \begin{aligned} A_{v} & =-G_{m}\left(R_{O} \| R_{O} ight) \ & =-2(6912 \| 6912)=-6912 \mathrm{~V} / \mathrm{V} \end{aligned}$

Figure 8.3.2
(a) Refer to Figure 8.3.2. For

\left|V_{t p} ight|=0.4 \mathrm{~V}

and

\left|V_{O V} ight|=0.2 \mathrm{~V}, V_{S G}=0.6 \mathrm{~V}

and the minimum required

V_{S D}

for each transistor is

0.2 \mathrm{~V}

. Thus,

V_{G 1}=+1.2 \mathrm{~V}, \quad V_{G 2}=+1.0 \mathrm{~V}, \quad

and

\quad V_{G S}=+0.8 \mathrm{~V}

(b)

\begin{aligned}I_{D} & =\frac{1}{2} \mu_{p} C_{O x}\left(\frac{W}{L} ight)\left|V_{O V} ight|^{2} \0.2 & =\frac{1}{2} imes 0.1 imes \frac{W}{L} imes 0.2^{2} \\Rightarrow \frac{W}{L} & =100\end{aligned}

(c)

\begin{aligned}r_{o 1} & =\frac{\left|V_{A} ight|}{I_{D}}=\frac{\left|V_{A}^{\prime} ight| L}{I_{D}}=\frac{6 imes 0.4}{0.2}=12 \mathrm{k} \Omega \r_{o 2} & =r_{o 3}=r_{o 1}=12 \mathrm{k} \Omega \g_{m 2} & =g_{m 3}=\frac{2 I_{D}}{\left|V_{O V} ight|}=\frac{2 imes 0.2}{0.2}=2 \mathrm{~mA} / \mathrm{V} \R_{o 2} & =\left(g_{m 2} r_{o 2} ight) r_{o 1}=(2 imes 12) imes 12=288 \mathrm{k} \Omega \R_{o 3} & =\left(g_{m 3} r_{o 3} ight) R_{o 2}=(2 imes 12) imes 288=6912 \mathrm{k} \Omega\end{aligned}

(d)

v_{O \max }=0.8+0.4=+1.2 \mathrm{~V}

(e)

\begin{aligned}A_{v} & =-G_{m}\left(R_{O} \| R_{O} ight) \& =-2(6912 \| 6912)=-6912 \mathrm{~V} / \mathrm{V}\end{aligned}

Figure 831 Design the Double-Cascode Current Source Shown in Fig I=0.2 mAI=0.2 \mathrm{~mA}I=0.2 mA

Figure 831
Design the Double-Cascode Current Source Shown in Fig $I=0.2 \mathrm{~mA}$