A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as____________
A)switching condition
B)master slave condition
C)race around condition
D)edge triggered condition

Question

A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as____________  
A)switching condition
B)master slave condition
C)race around condition
D)edge triggered condition

Quizplus · Accepted Answer

The continuous switching between 0 and 1 in a JK flip-flop due to the feedback arrangement is known as the "race around condition." This occurs when the clock pulse is too long, allowing the outputs to change more than once during a single clock pulse.

A User Has Designed JK Flip Flop by Using the VHDL