Structural, data and control hazards typically require a processor pipeline to stall. Listed below are a series of optimization techniques implemented in a compiler or a processor pipeline designed to reduce or eliminate stalls due to these hazards. For each of the following optimization techniques, state which pipeline hazards it addresses and how it addresses it. Some optimization techniques may address more than one hazard, so be sure to include explanations for all addressed hazards.
(a) Branch Prediction
(b) Instruction Scheduling
(c) delay slots
(d) increasing availability of functional units (ALUs, adders etc)
(e) caches

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The Answer of Structural, data and control hazards typically require a processor pipeline to stall. Listed below are a series of optimization techniques implemented in a compiler or a processor pipeline designed to reduce or eliminate stalls due to these hazards. For each of the following optimization techniques, state which pipeline hazards it addresses and how it addresses it. Some optimization techniques may address more than one hazard, so be sure to include explanations for all addressed hazards.
(a) Branch Prediction
(b) Instruction Scheduling
(c) delay slots
(d) increasing availability of functional units (ALUs, adders etc)
(e) caches

Structural, Data and Control Hazards Typically Require a Processor Pipeline