Deck 13: Flip-Flops, Shift Operators, and Finite State Machines Fsm in VHDL

Question 1

Which of the following flip-flop is used by the ring counter?

A)d flip-flops
B)sr flip-flops
C)jk flip-flops
D)t flip-flops

Answer 1

d flip-flops

Question 2

'shift_reg' is used to initialize the  

A)lsb
B)msb
C)register type
D)register bits

Answer 2

msb

Question 3

How many types of shift operators are there in VHDL?

A)three
B)four
C)five
D)six

Answer 3

six

Question 4

How many types of the data type are there in the ring counter?

A)one
B)two
C)three
D)more than three

Question 5

In counter universal clock is not used.

A)synchronous counter
B)asynchronous counter
C)decade counter
D)ring counter

Question 6

Synchronous counter use global clock, unlike asynchronous counter.

A)one
B)two
C)three
D)zero

Question 7

How many different states does a decade counter count?

A)eight
B)nine
C)ten
D)eleven

Question 8

Output values of Moore type FSM are determined by its                  

A)input values
B)output values
C)clock input
D)current state

Question 9

What happens if the input is high in FSM?

A)change of state
B)no transition in state
C)remains in a single state
D)invalid state

Question 10

What happens if the input is low in FSM?

A)change of state
B)no transition in state
C)remains in a single state
D)invalid state

Question 11

In FSM diagram what does circle represent?

A)change of state
B)state
C)output value
D)initial state

Question 12

In the FSM diagram, what does arrow between the circles represent?

A)change of state
B)state
C)output value
D)initial state

Question 13

In the FSM diagram, what does the information below the line in the circle represent?

A)change of state
B)state
C)output value
D)initial state

Question 14

Moore machine has states than a mealy machine.

A)fewer
B)more
C)equal
D)negligible

Question 15

State transition happens in every clock cycle.

A)once
B)twice
C)thrice
D)four times

Question 16

Output values of mealy type FSM are determined by its                  

A)input values
B)output values
C)both input values and current state
D)current state

Question 17

What kind of output does mealy machine produce?

A)asynchronous
B)synchronous
C)level
D)pulsed

Question 18

States in FSM are represented by                  

A)bits
B)bytes
C)word
D)character

Question 19

What is the first step in writing the VHDL for an FSM?

A)to define the vhdl entity
B)naming the entity
C)defining the data type
D)creating the states

Question 20

Which of the following react faster to inputs?

A)sequencer
B)generators
C)mealy machines
D)moore machines

Question 21

What is the first state of FSM?

A)wait loop state
B)initial state
C)output state
D)activate pulse state

Question 22

Mealy machines have states than Moore machine.

A)fewer
B)more
C)equal
D)negligible

Question 23

In mealy type FSM, the path is labelled by which of the following?

A)inputs
B)outputs
C)both inputs and outputs
D)current state

Question 24

The process statement used in combinational circuits is called process.

A)combinational
B)clocked
C)unclocked
D)sequential

Question 25

Why we need to include all the input signals in the sensitivity list of the process?

A)to monitor the output continuously
B)to monitor the input continuously
C)to make the circuit synthesizable by eda tools
D)no special purpose