Deck 9: Registers and Counters in Digital Logic

Question 1

When both inputs of SR latches are high, the latch goes______________      

A)unstable
B)stable
C)metastable
D)bistable

Answer 1

metastable

Question 2

The register is a type of______________      

A)sequential circuit
B)combinational circuit
C)cpu
D)latches

Answer 2

sequential circuit

Question 3

How many types of registers are?

A)2
B)3
C)4
D)5

Answer 3

4

Question 4

The main difference between a register and a counter is______________      

A)a register has no specific sequence of states
B)a counter has no specific sequence of states
C)a register has capability to store one bit of information but counter has n-bit
D)a register counts data

Question 5

In serial shifting method, data shifting occurs

A)universal shift register
B)unidirectional shift register
C)unipolar shift register
D)unique shift register

Question 6

A register that is used to store binary information is called______________      

A)data register
B)binary register
C)shift register
D)d - register

Question 7

A shift register is defined as______________      

A)the register capable of shifting information to another register
B)the register capable of shifting information either to the right or to the left
C)the register capable of shifting information to the right only
D)the register capable of shifting information to the left only

Question 8

In digital logic, a counter is a device which

A)counts the number of outputs
B)stores the number of times a particular event or process has occurred
C)stores the number of times a clock pulse rises and falls
D)counts the number of inputs

Question 9

A counter circuit is usually constructed of

A)a number of latches connected in cascade form
B)a number of nand gates connected in cascade form
C)a number of flip-flops connected in cascade
D)a number of nor gates connected in cascade form

Question 10

4 COUNTERS

A)0 to 2ⁿ
B)0 to 2ⁿ + 1
C)0 to 2ⁿ - 1
D)0 to 2^n+1/2

Question 11

How many types of the counter are there?

A)2
B)3
C)4
D)5

Question 12

A decimal counter has____________states.

A)5
B)10
C)15
D)20

Question 13

Ripple counters are also called______________        

A)ssi counters
B)asynchronous counters
C)synchronous counters
D)vlsi counters

Question 14

Synchronous counter is a type of______________        

A)ssi counters
B)lsi counters
C)msi counters
D)vlsi counters

Question 15

Three decade counter would have______________        

A)2 bcd counters
B)3 bcd counters
C)4 bcd counters
D)5 bcd counters

Question 16

BCD counter is also known as______________        

A)parallel counter
B)decade counter
C)synchronous counter
D)vlsi counter

Question 17

The parallel outputs of a counter circuit represent the______________          

A)parallel data word
B)clock frequency
C)counter modulus
D)clock count

Question 18

A sequential logic can't be executed by concurrent statements only.

Question 19

Which of the following sequential circuit doesn't need a clock signal?

A)flip flop
B)asynchronous counter
C)shift register
D)latch

Question 20

The following timing diagram shows____________flip flop.

A)t flip-flop
B)d flip-flop
C)sr flip-flop
D)jk flip-flop

Question 21

The process used for implementation of sequential logic in VHDL is called____________process.

A)sequential process
B)combinational process
C)clocked process
D)unclocked process

Question 22

Why do we need to define clock signal in the sensitivity list of the process?

A)to trigger the statement as soon as there is some event on clock
B)to trigger the clock signal as soon as there is some event on input
C)to trigger the clock signal as soon as there is some event on output
D)to trigger the statement as soon as there is some event on input

Question 23

A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as____________  

A)switching condition
B)master slave condition
C)race around condition
D)edge triggered condition

Question 24

Which of the following method is not used to remove the race around condition in a flip flop?

A)using level triggered flip flop
B)using master slave flip flop
C)using edge triggered flip flop
D)all of the above are used to remove the race around

Question 25

Which of the following attribute is generally used in implementation of sequential circuits?

A)'stable
B)'length
C)'last_event
D)'event