Deck 2: Understanding Cache Memory and Its Implementation

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Question
The reason for the implementation of the cache memory is _________      

A)To increase the internal memory of the system
B)The difference in speeds of operation of the processor and memory
C)To reduce the memory access and cycle time
D)All of the mentioned
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Question
The correspondence between the main memory blocks and those in the cache is given by _________        

A)Hash function
B)Mapping function
C)Locale function
D)Assign function
Question
The approach where the memory contents are transferred directly to the processor from the memory is called _________  

A)Read-later
B)Read-through
C)Early-start
D)None of the mentioned
Question
The algorithm to remove and place new contents into the cache is called _________    

A)Replacement algorithm
B)Renewal algorithm
C)Updation
D)None of the mentioned
Question
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is _________  

A)0.0021
B)0.0038
C)0.0064
D)0.0128
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Deck 2: Understanding Cache Memory and Its Implementation
1
The reason for the implementation of the cache memory is _________      

A)To increase the internal memory of the system
B)The difference in speeds of operation of the processor and memory
C)To reduce the memory access and cycle time
D)All of the mentioned
The difference in speeds of operation of the processor and memory
2
The correspondence between the main memory blocks and those in the cache is given by _________        

A)Hash function
B)Mapping function
C)Locale function
D)Assign function
Mapping function
3
The approach where the memory contents are transferred directly to the processor from the memory is called _________  

A)Read-later
B)Read-through
C)Early-start
D)None of the mentioned
Early-start
4
The algorithm to remove and place new contents into the cache is called _________    

A)Replacement algorithm
B)Renewal algorithm
C)Updation
D)None of the mentioned
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5
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is _________  

A)0.0021
B)0.0038
C)0.0064
D)0.0128
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