Deck 6: System Integration and Performance

Question 1

A buffer for an I/O device is typically implemented on the sending computer.

Answer 1

False

Question 2

When multiple processors occupy a single motherboard, they share primary storage and a single system bus.

Answer 2

True

Question 3

Secondary storage devices are much faster than the system bus.

Answer 3

False

Question 4

Disk caching is common in modern computer systems, particularly in file and database servers.

Question 5

A system bus can be conceptually or physically divided into specialized subsets, including the data, address, control, and power buses.

Question 6

The CPU communicates with a peripheral device by moving data to or from an I/O port's dedicated bus.

Question 7

A full-featured 64-bit CPU, even one with multiple ALUs and pipelined processing, typically requires fewer than 50 million transistors.

Question 8

A PC usually transmits data one bit at a time over a wireless connection, and a laser printer prints an entire page at once.

Question 9

​A system bus connects computer system components, including the CPU, memory, storage, and I/O devices.

Question 10

​Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement.

Question 11

Peer-to-peer bus protocols are substantially less complex but more expensive than master-slave bus protocols.

Question 12

During a write operation, a cache acts similarly to a buffer.

Question 13

The OS is the best source of file access information because it updates information dynamically as it services file access requests.

Question 14

Data written to a cache during a write operation isn't automatically removed from the cache after it's written to the underlying storage device.

Question 15

With serial communication lines in a bus, each line carries only one bit value or signal at a time, and many lines are required to carry data, address, and control bits.

Question 16

Until the 2000s, system buses were always constructed with serial electrical lines.

Question 17

One way to limit wait states is to use an SDRAM cache between the CPU and SRAM primary storage.

Question 18

The memory bus has a much higher data transfer rate than the system bus because of its shorter length, higher clock rate, and (in most computers) large number of parallel communication lines.

Question 19

Serial channels in buses are more reliable than parallel channels at very high speeds.

Question 20

Devices with low data transfer demand can use a single PCI bus lane, and devices with higher requirements can increase their available data transfer rate by using additional lanes.

Question 21

A ____ is a simple processor attached to a peer-to-peer bus that decides which devices must wait when multiple devices want to become a bus master.

A) bus master unit
B) bus arbitration unit
C) bus controller
D) bus interface

Question 22

People routinely download megabytes or gigabytes of data via the Internet and store gigabytes of data on handheld devices, terabytes on desktop computers, and petabytes to exabytes in corporate and government data centers.

Question 23

​A ____ is a shared electrical or optical channel that connects two or more devices.
C) ​Route
D) ​connection

Question 24

When the CPU is the focus of all computer activity, all other devices are ____.

A) bus masters
B) bus primates
C) bus limiters
D) bus slaves

Question 25

Zip files and archives are examples of lossless compression.

Question 26

Devices attached to a system bus coordinate and synchronize their activities with a common ____.

A) bus clock
B) control bus
C) data bus
D) system bus

Question 27

In a ____, any device can assume control of the bus or act as a bus master for transfers to any other device.

A) peer-to-peer bus
B) star bus
C) linear bus
D) ring bus

Question 28

The ____ governs the format, content, and timing of data, memory addresses, and control messages sent across the bus.

A) bus clock
B) bus size
C) bus protocol
D) bus master

Question 29

Both multicore and multiple-processor architectures are examples of scaling up because they increase the power of a single computer system.

Question 30

Under direct memory access, a device called a ____ is attached to the bus and to main memory.

A) controller
B) DMA master
C) DMA controller
D) DRM controller

Question 31

Lossless compression ratios higher than 50:1 are difficult or impossible to achieve with audio and video data.

Question 32

Until the 1990s, scaling up was almost always a more cost-effective strategy to increase available computer power because communication between computers was extremely slow compared with communication between a single computer's components.

Question 33

Multiple-processor architecture is not common in workstations.

Question 34

The ____ carries commands, command responses, status codes, and similar messages.

A) bus clock
B) command bus
C) CPU
D) control bus

Question 35

There are typically multiple storage and I/O devices connected to a computer, collectively referred to as ____.

A) core devices
B) peripheral devices
C) perimeter devices
D) companion devices

Question 36

The largest computational problems, such as those encountered in modeling three-dimensional physical phenomena, can be solved by a single computer as long as it has enough computing resources.

Question 37

When the CPU is the focus of all computer activity, it's also the ____.

A) bus clock
B) bus master
C) bus slave
D) bus protocol

Question 38

Using data compression alters the balance of processor resources and communication or storage resources in a computer system.

Question 39

Reducing the size of stored or transmitted data can improve performance whenever there's a dearth of processing power.

Question 40

MP3 compresses the audio data stream by discarding information about masked sounds or representing them with fewer bits.

Question 41

The main goal of buffering and caching is to ____.

A) control data channels
B) improve I/O performance
C) improve overall system performance
D) reduce system load

Question 42

Most performance benefits of a cache occur during ____.

A) write operations
B) mixed operations
C) buffered operations
D) read operations

Question 43

If the CPU is idle while a device completes an access request, the CPU cycles that could have been (but weren't) devoted to instruction execution are called ____.

A) I/O channels
B) I/O hooks
C) I/O wait states
D) I/O peers

Question 44

____ is a family of bus standards found in nearly all small and midrange computers and many larger ones.

A) Peripheral Component Interface
B) Peripheral Connection Interface
C) Peripheral Component Interconnect
D) Peripheral Component Interchange

Question 45

A ____ is a processor that guesses what data will be requested in the near future and loads this data from the storage device into the cache before it's actually requested.

A) cache miss
B) cache controller
C) cache hit
D) cache algorithm

Question 46

When three cache levels are in use, the cache farthest from the CPU is called a ____ cache.

A) level zero
B) level one
C) level two
D) level three

Question 47

The ____ states that when multiple resources are required to produce something useful, adding more of a single resource produces fewer benefits.

A) law of regression
B) law of diminishing returns
C) law of diminished value
D) law of diversity

Question 48

As buffer size increases above ____ bytes, CPU cycle consumption decreases at a linear rate.

A) 4
B) 8
C) 12
D) 16

Question 49

Data, address, and command bits are transmitted across PCI bus line subsets called "____."

A) lanes
B) ports
C) stripes
D) bundles

Question 50

When the data needed isn't in the cache, the access is called a ____.

A) cache hit
B) cache fault
C) cache miss
D) cache pull

Question 51

The ____ connects only the CPU and memory.

A) storage bus
B) local bus
C) system bus
D) memory bus

Question 52

A ____ connects secondary storage devices to the system bus.

A) memory bus
B) storage bus
C) system bus
D) local bus

Question 53

A(n) ____ is a communication pathway from the CPU to a peripheral device.

A) connection port
B) I/O port
C) device port
D) block port

Question 54

One task performed by a storage device controller is translating logical write operations into ____ write operations.

A) stack
B) bugger
C) cache
D) physical

Question 55

The ratio of cache hits to read accesses is called the cache's ____.

A) hit ratio
B) efficiency
C) Performance
D) hit boundary

Question 56

When three cache levels are in use, the cache closest to the CPU is called a ____ cache.

A) level zero
B) level one
C) level two
D) level three

Question 57

Many computer system designers rely on ____ to implement disk caching.

A) the OS
B) specialized disk controller hardware
C) applications
D) firmware

Question 58

If a buffer isn't large enough to hold and entire unit of data transfer, an error called a ____ occurs.

A) buffer overflow
B) buffer underflow
C) heap overflow
D) buffer fault

Question 59

In most computers, an I/O port is a ____.

A) system address
B) memory block
C) network device
D) memory address

Question 60

A ____ is a reserved area of main memory accessed on a last-in, first-out (LIFO) basis.

A) stack
B) queue
C) chain
D) heap

Question 61

In the simplest sense, a(n) ____________________ is just a set of communication lines.

Question 62

In traditional computer architecture, the ____________________ is the focus of all computer activity.

Question 63

____ is a technique that reduces the number of bits used to encode data, such as a file or a stream of video images transmitted across the Internet.

A) Compression
B) Dispersion
C) Randomization
D) Coordination

Question 64

Storage and I/O devices are normally connected to the system bus or a subsidiary bus through a(n) ____________________.

Question 65

The ____________________ bus improves computer system performance by removing video traffic from the system bus and providing a high-capacity one-way communication channel optimized for video data.

Question 66

Lossy compression of audio and video can achieve compression ratios up to ____.

A) 25:1
B) 50:1
C) 75:1
D) 100:1

Question 67

​The ____________________ transmits data between computer system components.

Question 68

The latest trend in high-performance CPU design embeds multiple CPUs and cache memory on a single chip-an approach called ____.

A) multiple-processor architecture
B) multicore architecture
C) multipath architecture
D) partial execution architecture

Question 69

____________________ buses connect a subset of computer components and are specialized for these components' characteristics and communication between them.

Question 70

With ____ compression, any data input that's compressed and then decompressed is exactly the same as the original input.

A) lossy
B) lossless
C) perfect
D) ideal

Question 71

____ is a cost-effective approach to computer system design when a single computer runs many different application programs or services.

A) Partial execution architecture
B) Multipath architecture
C) Multicore architecture
D) Multiple-processor architecture

Question 72

With ____ compression, data inputs that are compressed and then decompressed are different from, but still similar to, the original input.

A) lossy
B) lossless
C) universal
D) ideal

Question 73

The ____________________ distributes electrical power to directly attached devices or their device controllers.

Question 74

____________________ ports enable the CPU and bus to interact with a keyboard in the same way they interact with a disk drive or video display.

Question 75

A ____ is a mathematical compression technique implemented as a program.

A) compression system
B) compression routine
C) compression utility
D) compression algorithm

Question 76

____ is an approach that partitions processing and other tasks among multiple computer systems.

A) Scaling up
B) Scaling down
C) Scaling out
D) Scaling in

Question 77

The phrase ____ describes approaches to increasing processing and other computer system power by using larger and more powerful computers.

A) scaling out
B) scaling up
C) scaling down
D) scaling wide

Question 78

Computer system components coordinate their activities by sending signals over the ____________________.

Question 79

The term ____ describes the ratio of data size in bits or bytes before and after compression.

A) compression value
B) compression efficiency
C) compression ratio
D) compression ratio

Question 80

A(n) ____________________ bus, such as a Universal serial Bus, connects one or more external devices to the system bus.